PXF4336 Datasheet, PDF (258/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

7.2.12
ABM-P
PXF 4336 V1.1
Register Description
Queue Configuration Table Transfer Registers
Internal Table 4: Queue Configuration Table Transfer Registers QCT0..6
Queue Configuration Table Transfer Registers are used to access the internal Queue
Configuration Table (QCT) containing 2*8192 entries. The lower 8K entries control the
upstream core queues and the upper 8K entries control the downstream core queues.
Table 7-10 shows an overview of the registers involved. Some fields are not used for
entry 0 (common real time bypass)
Table 7-10 Registers for Queue Configuration Table Access
111
0
QCT RAM entry
15 0 15 0 15 0 15 0 15 0 15 0 15 0
QCT6 QCT5 QCT4 QCT3 QCT2 QCT1 QCT0
15 0 15 0 15 0 15 0 15 0 15 0 15 0
MASK6 MASK5 MASK4 MASK3 MASK2 MASK1 MASK0
=FFFF_H =FFFF_H =FFFF_H =FFFF_H
=FFFF_H
RAM
select:
15 0
MAR=02_H
Queue
select:
15 0
WAR
(0..16383_D)
QCT0...QCT6 are the transfer registers for one 112 bit QCT table entry. The core
selection and queue number representing the table entry which needs to be read or
written must be written to the Word Address Register (WAR). The dedicated QCT table
entry is read into the QCT0..QCT6 registers or modified by the QCT0..QCT6 register
values with a write mechanism. The associated Mask Registers MASK0..MASK6 allow
a bit-wise Write operation (0 - unmasked, 1 - masked). In case of Read operation, the
dedicated QCT0..QCT6 register bit will be overwritten by the respective QCT table entry
bit value. In case of Write operation, the dedicated QCT0..QCT6 register bit will modify
the respective QCT table entry bit value.
Note: It is recommended not to Write to bit fields (111:64) and (15:0) of the QCT table
entries; i.e. registers MASK0, MASK6, MASK5, MASK4 and MASK3 should
always be programmed with FFFF_H.
The 13 LSBs (= Bit 12..0) of the WAR register select the queue-specific entry that will be
accessed and bit ’CoreSel’ the ABM-P core.
The Read or Write process is controlled by the Memory Address Register (MAR). The 5
LSBs (= Bit 4..0) of the MAR select the memory/table that will be accessed; to select the
QCT table, bit field MAR(4:0) must be set to 2. Bit 5 of MAR starts the transfer and is
automatically cleared after execution.
Data Sheet
258
2001-12-17