PXF4336 Datasheet, PDF (12/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

ABM-P
PXF 4336 V1.1
List of Figures
Page
Figure 3-48
Figure 3-49
Figure 3-51
Figure 3-52
Figure 4-1
Figure 4-7
Figure 4-9
Figure 4-12
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 5-7
Figure 5-8
Figure 5-9
Figure 5-10
Figure 7-1
Figure 8-1
Figure 8-2
Figure 8-3
Figure 8-4
Figure 8-5
Figure 8-6
Figure 8-7
Figure 8-8
Figure 8-9
Figure 8-10
Figure 8-11
Figure 8-12
Figure 8-13
Figure 9-1
Message Interface between ERC Unit and ABM-P Core. . . . . . . . . . 111
SCAN Timer Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table Access Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
AVT Context RAM Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . 119
Parameters for Connection Setup (bit field width indicated) . . . . . . . 133
ABM-P Application Example: DSLAM . . . . . . . . . . . . . . . . . . . . . . . . 147
Example of Threshold Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 150
AAL5 Extraction: End of packet, Trailer and Status Byte. . . . . . . . . . 157
UTOPIA Receive Upstream Master Mode . . . . . . . . . . . . . . . . . . . . . 159
UTOPIA Receive Upstream Slave Mode . . . . . . . . . . . . . . . . . . . . . . 159
UTOPIA Transmit Downstream Master Mode . . . . . . . . . . . . . . . . . . 161
UTOPIA Transmit Downstream Slave Mode . . . . . . . . . . . . . . . . . . . 161
Intel Style Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Intel Style Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Motorola Style Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Motorola Style Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SPI Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
QCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table Access Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Input/Output Waveform for AC Measurements . . . . . . . . . . . . . . . . . 401
Microprocessor Interface Write Cycle Timing (Intel) . . . . . . . . . . . . . 403
Microprocessor Interface Read Cycle Timing (Intel) . . . . . . . . . . . . . 404
Microprocessor Interface Write Cycle Timing (Motorola) . . . . . . . . . . 405
Microprocessor Interface Read Cycle Timing (Motorola). . . . . . . . . . 406
Setup and Hold Time Definition (Single- and Multi-PHY). . . . . . . . . . 408
Tristate Timing (Multi-PHY, Multiple Devices Only) . . . . . . . . . . . . . . 408
SSRAM Interface Generic Timing Diagram . . . . . . . . . . . . . . . . . . . . 413
Generic SDRAM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . 414
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Boundary-Scan Test Interface Timing Diagram . . . . . . . . . . . . . . . . . 416
SPI Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
QCI Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Block Diagram of Test Access Port and Boundary Scan Unit . . . . . . 420
Data Sheet
12
2001-12-17