PXF4336 Datasheet, PDF (50/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

ABM-P
PXF 4336 V1.1
Functional Description
3.2.4 AAL5 Assistant
The AAL5 Assistant unit allows insertion and extraction of AAL5 segmented packets
from and towards the Microprocessor Interface. Supported by the corresponding
software driver, the unit implements an “in-line” SAR function, i.e. one packet is
processed at any time by an SAR function. However, upstream and downstream flow as
well as extraction and insertion are independent functions that may be operationally
interleaved.
For extraction, a Scheduler Block must be associated to the AAL5 Assistant unit and
each queue assigned to this scheduler block must be assigned to a VC-merge group to
guarantee that complete packets are forwarded to the AAL5 Assistant unit. The
scheduler block rates can be adjusted according to the microprocessor interface
bandwidth or the intended CPU load. However, the CPU may extract the payload chunks
at a lower rate which will result in internal scheduler block backpressure. No data loss
will occur in that case. The CPU reads consecutive bytes from the cell’s payload chunks
that can be re-assembled immediately in the host memory while the AAL5 Assistant unit
checks the AAL5 trailer. The section “AAL5 Packet Extraction” on Page 156 provides
programming details.
Refer to “Scheduler Configuration Table Integer Transfer Registers” on Page 306
for the assignment of scheduler blocks to the AAL5 Assistant and the programming of
their rates.
For insertion, the CPU prepares the ATM cell header for the following packet and writes
packet payload chunks to the AAL5 Assistant unit which will generate the cells and the
AAL5 trailer for automatic completion of the last cell of the packet. Internally, the cells
are forwarded to either the downstream or upstream Cell Handler and processed in the
same way as cells received by an UTOPIA receive interface.
The section “AAL5 Packet Insertion” on Page 156 provides the details.
3.2.5 Internal Address Reduction Unit
The ABM-P requires an internal 16-bit Local Connection Identifier (LCI) to address its
resources. Two basic cell addressing schemes are supported to extract/generate an LCI
from the cell header:
• LCI Mapping Modes
An external device generates an LCI and maps it into the ATM cell header. Three
different mapping modes are supported by the ABM-P.
The LCI mapping modes are described as part of the UTOPIA interface description in
chapters “UTOPIA L2 Interfaces (PHY side)” on Page 159 and “UTOPIA L2
Interface (Backplane side)” on Page 169.
• Internal Address Reduction Mode
The ABM-P generates its own internal LCI as a programmable combination of the cell
Data Sheet
50
2001-12-17