PXF4336 Datasheet, PDF (178/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

ABM-P
PXF 4336 V1.1
Interface Description
• Periodic Frame Mode:
The pattern is periodically transmitted with an HDLC framing. The transmit clock is
provided externally.
• Single Step Frame Mode:
A single pattern is transmitted with an HDLC framing if the ‘QCITXFRAME’ signal is
asserted. The transmit clock is provided externally.
The bit-stuffing function is optional. The HDLC frame is transmitted-octet synchronous
starting with the ‘QCITXFRAME’ signal. The ‘QCITXFRAME’ signal may not be asserted
for more than 3 clock cycles. The minimum distance between two frames has to be
payload-length + 16 + 1 or even more if bitstuffing is used.
QueueThresholdIndication(8191..0)
Table QTI
012
8190 8191
read
Mini HDLC Engine
N-1
Frame N
N+1
7Eh 7Eh
1024 Byte (Payload); opt. bit-stuffing
CRC16 7Eh 7Eh
QCI Interface
Note:
1k queues: 128 byte payload
2k queues: 256 byte payload
4k queues: 512 byte payload
8k queues:1024 byte payload
QCITXFRAME
QCITXCLK
QCITXDAT
Note:
At 60 MHz, a complete pattern is
transmitted in appr. 0.138ms.
Figure 5-10 QCI Interface
The bit-pattern length can be limited to 1k, 2k, 4k or 8k (maximum number of
downstream queues). The first data bit of the pattern always represents the threshold
status of queue 0, the second bit represents queue 1 respectively (increasing order).
Data Sheet
178
2001-12-17