PXF4336 Datasheet, PDF (409/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

ABM-P
PXF 4336 V1.1
Electrical Characteristics
In the following tables, AÞP (column DIR, Direction) defines a signal from the ATM
Layer (transmitter, driver) to the PHY Layer (receiver), A⇐P defines a signal from the
PHY Layer (transmitter, driver) to the ATM Layer (receiver).
Both UTOPIA Interfaces (PHY-side and Backplane-side) can be configured in either
Slave or Master Mode. If configured in Master Mode, the interface is considered to be
the ATM Layer device (A) and if configured in Slave Mode, the interface is considered to
be the PHY Layer device (P) respectively.
All timings also apply to UTOPIA Level 1 8-bit data bus operation.
•
Table 8-9 Transmit Timing (16-Bit Data Bus, 50 MHz Cell Mode, Single PHY)
No. Signal Name DIR Description
Limit Values Unit
Min
Max
80 UTXCLKD, A>P TxClk frequency (nominal) 0
52
MHz
81 ^UTXCLKU
TxClk duty cycle
40
60
%
82
TxClk peak-to-peak jitter
-
5
%
83
TxClk rise/fall time
-
2
ns
84 UTXDATD, A>P Input setup to TxClk
4
-
ns
85
UTXDATU,
UTXPRTYD,
Input hold from TxClk
1
-
ns
UTXPRTYU,
UTXSOCD,
UTXSOCU,
UTXENBD,
UTXENBU
86 UTXCLAVD, A<P Input setup to TxClk
4
-
ns
87 ^UTXCLAVU
Input hold from TxClk
1
-
ns
•
Table 8-10 Receive Timing (16-Bit Data Bus, 50 MHz Cell Mode, Single PHY)
No. Signal Name DIR Description
Limit Values Unit
Min
Max
80 URXCLKD, A>P RxClk frequency (nominal)
URXCLKU
URXCLKD:
0
URXCLKU:
0
MHz
60
52
81
RxClk duty cycle
40
60
%
82
RxClk peak-to-peak jitter
-
5
%
83
RxClk rise/fall time
-
2
ns
Data Sheet
409
2001-12-17