PXF4336 Datasheet, PDF (262/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

VS/VDen
ABM-P
PXF 4336 V1.1
Register Description
’1’
The queue is always scheduled/re-scheduled with its
specific rate independent of the queue filling level.
Scheduling an empty queue results in an ’empty cell
cycle’ (no cell is emitted during this cycle).
A so called ’dummy queue’ is used either for generating
empty cell cycles or by the ERC unit for generating out-
of-rate RM cells.
Note: ’RSall’ can be set with connection setup (together
with QIDvalid=’1’) or anytime while the queue is
enabled.
After setting bit ’RSall’, the ABM-P will
automatically set bit ’MGconf/DQsch’ to
acknowledge the first dummy schedule event.
The ’RSall’ information is internally conveyed to
the scheduler. This process is acknowledged by
an interrupt (Bit ’UDQRD/DDQRD’ in Register
117: ISRC). It is recommended not to select any
other table or table entry while waiting for this
acknowledge.
Note: ’RSall’ can be reset anytime while the queue is
enabled. In response to resetting ’RSall’ the
ABM-P will generate an interrupt (Bit ’UDQRD/
DDQRD’ in Register 117: ISRC) and reset bit
’MGconf/DQsch’ in this table.
Note: To activate or deactivate a dummy queue, command bit
’DQac’ must be set in conjunction with setting or resetting bit
’RSall’.
VS/VD Enable
This bit enables ABR VS/VD operation for the queue (in conjunction
with appropriate settings of the ERC unit):
’0’
The queue is not configured for ABR VS/VD operation.
’1’
The queue is configured for ABR VS/VD operation in
conjunction with proper settings of the ERC unit.
This bit enables control information exchange between
the Buffer Manager and the ERC unit as well as enables
ABR OAM cell handling.
Data Sheet
262
2001-12-17