PXF4336 Datasheet, PDF (370/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

Register 124 WAR
Word Address Register
ABM-P
PXF 4336 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
WAR
EC_H
Written by CPU to address entries of internal RAM/
tables for Read or Write operation via transfer registers.
Bit
15
14
13
12
11
10
9
8
WAR(15:8)
Bit
7
6
5
4
3
2
1
0
WAR(7:0)
WAR(15:0)
Word Address
This bit field selects an entry within the internal RAM/table selected
by the MAR register.
In general, it can address up to 64K entries.
The current range of supported values depends on the size and
organization of the selected RAM/table.
Thus, the specific WAR register meaning is listed in the overview
part of each internal RAM/table description:
LCI
LCI Table RAM (see page 237)
TCT
Traffic Class Table (see page 241)
QCT
Queue Configuration Table (see page 270)
SBOC Scheduler Block Occupation Table (see page 270)
QPTHU QPT High Word Upstream:
Queue Parameter Table (see page 296f.)
QPTHD QPT High Word Downstream:
Queue Parameter Table (see page 296f.)
QPTLU QPT Low Word Upstream:
Queue Parameter Table(see page 296)
QPTLD QPT Low Word Downstream:
Queue Parameter Table (see page 296)
Data Sheet
370
2001-12-17