PXF4336 Datasheet, PDF (241/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

7.2.11 Traffic Class Table Transfer Registers
ABM-P
PXF 4336 V1.1
Register Description
Internal Table 3: Traffic Class Table Transfer Registers TCT0, TCT1, TCT2, TCT3
The Traffic Class Table Transfer Registers are used to access the internal Traffic Class
Table (TCT) containing 2*16 entries of 4*64 bits each (16 traffic classes per ABM-P core,
4 words of 64 bits per entry). Table 7-8 shows an overview of the registers involved.
Table 7-8 Registers for TCT Table Access
63
0
TCT RAM entry
15
0 15
0 15
0 15
0
TCT3
TCT2
TCT1
TCT0
15
0 15
0 15
0 15
0
MASK3
MASK2
MASK1
MASK0
RAM select:
15
0
MAR=01_H
TCT entry select:
15
0
WAR (0..127_D)
TCT0, TCT1, TCT2 and TCT3 are the transfer registers used to access the 4*64 bit TCT
table entries.
Core selection, traffic class number, and 64-bit word selection of the table entry which
needs to be read or written must be programmed to the Word Address Register (WAR).
The dedicated TCT table entry 64-bit word is read into the TCT3/TCT2/TCT1/TCT0
registers or modified by the TCT3/TCT2/TCT1/TCT0 register values with a write
mechanism. The associated Mask Registers MASKi (i=3..0) allow a bit-wise masking for
Write operation (0 - unmasked, 1 - masked). In case of Read operation, the dedicated
TCTi (i=3..0) register bit will be overwritten by the respective TCT table entry bit value.
In case of Write operation, the dedicated TCTi (i=3..0) register bit will modify the
respective TCT table entry bit value.
The Read or Write process is controlled by the Memory Address Register (MAR). The 5
LSBs (= Bit 4..0) of the MAR select the memory/table that will be accessed; to select the
TCT table bit field MAR(4:0) must be set to 1. Bit 5 of MAR starts the transfer and is
automatically cleared after execution.
Data Sheet
241
2001-12-17