PXF4336 Datasheet, PDF (231/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

7.2.9 DBA Control Registers
ABM-P
PXF 4336 V1.1
Register Description
Register 31 DSBT1
Upstream/Downstream DBA Scheduler Block Threshold Register 1
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
FFFF_H
DSBT1
36_H
Written and Read by CPU during initialization
Bit
15
14
13
12
11
10
9
8
DSBT1HP(11:4)
Bit
7
6
5
4
3
2
1
0
DSBT1LP(11:4)
DSBT1HP(11:4)
DSBT1LP(11:4)
DBA Scheduler Block Threshold 1 High Priority
This bit field represents the most significant 8 bits of the internal
12-bit wide High Priority DBA Threshold 1. The threshold value is
global, but individually evaluated against all scheduler block
specific fill level counter (upstream and downstream) of the same
priority class (SBOccHP).
The threshold range is (0..4095) with a granularity of 16 cells.
The CPU programs the threshold with a granularity of 4 cells by
right shifting the value by 4:
DSBT1HP(11:4):= (threshold_value >> 4)
DBA Scheduler Block Threshold 1 Low Priority
This bit field represents the most significant 8 bits of the internal
12-bit wide Low Priority DBA Threshold 1. The threshold value is
global, but individually evaluated against all scheduler block
specific fill level counter (upstream and downstream) of the same
priority class (SBOccLP).
The threshold range is (0..4095) with a granularity of 16 cells.
The CPU programs the threshold with a granularity of 4 cells by
right shifting the value by 4:
DSBT1LP(11:4):= (threshold_value >> 4)
Data Sheet
231
2001-12-17