PXF4336 Datasheet, PDF (264/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

Register 45 QCT2
Queue Configuration Transfer Register 2
ABM-P
PXF 4336 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
QCT2
44_H
Written by CPU to configure VC-Merge operation
Bit
15
14
13
12
11
10
9
8
MGconf/
DQsch
MGID(6:0)
Bit
7
6
5
4
3
2
1
0
MinBG(7:0)
MGconf/DQsch
Merge Group Configured/
Dummy Queue Scheduled
The meaning of this flag depends on bit ’RSall’:
RSall=’0’
The queue is not configured as a ’dummy queue’ and may be
configured as a VC-merge group member:
MGconf
0
The queue is neither a dummy queue, nor member of a
VC-merge group.
1
The queue is member of a VC-merge group. The VC-
merge group is determined by bit field ’MGID(6:0).
Note: To disable an active VC-merge group, bit
’QIDvalid’ must be reset. Deactivating the queue
by setting QIDvalid=’0’ automatically starts an
internal process to delete the queue from the VC-
merge group. In response to resetting ’QIDvalid’
the ABM-P will generate an interrupt (Bit
’UQVCMGD/DQVCMGD’ in Register 117: ISRC)
and reset bit ’MGconf/DQsch’ in this table.
RSall=’1’
The queue is configured as a ’dummy queue’:
DQsch
Data Sheet
264
2001-12-17