PXF4336 Datasheet, PDF (373/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

Register 126 MODE1
ABM-P Mode 1 Register
ABM-P
PXF 4336 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
MODE1
EE_H
Written and Read by CPU
Bit
15
14
SWRES ^ERC
SWRES
13
12
CPR(1:0)
11
VC
MERGE
10
INIT
RAM
9
INIT
SDRAM
8
CORE
Bit
7
6
5
4
3
2
1
0
WGS
BIN
EFCI BIP8 CRC10 LCItog LCIMOD(1:0)
SWRES
Software Reset (clears automatically after four cycles).
This bit is automatically cleared after execution.
’SWRES’ controls reset of all ABM-P units excluding the ERC unit.
1
Starts internal reset procedure
(0)
self-clearing
ERCSWRES
ERC Software Reset (not self-clearing).
’ERCSWRES’ controls reset of the ERC unit.
1
Starts internal reset procedure and keeps the ERC unit
in reset state.
0
Releases the ERC unit from reset state to operational
state.
CPR(1:0)
Cell Pointer Ram Size configuration
(see also Table 7-3 "External RAM Sizes" on Page 215)
00
256k pointer entries per direction
(corresponds to 256k cells in each cell storage RAM)
01
128k pointer entries per direction
(corresponds to 128k cells in each cell storage RAM)
Data Sheet
373
2001-12-17