PXF4336 Datasheet, PDF (235/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

ABM-P
PXF 4336 V1.1
Register Description
Internal Table 1: DBA Threshold Crossing Table Transfer Register
The DBA Threshold Crossing Table (DTCT) Transfer Register is used to access the
internal Upstream/Downstream DBA Threshold Crossing Table containing 2*8 entries of
16 bits each. Table 7-4 summarize the registers.
Table 7-4 Registers DTC Upstream/Downstream Table Access
15
0
DTCT RAM Entry
RAM Select:
15
0
15
0
DTCT
MAR=05_H
Entry Select:
15
0
no Mask;
read access only
WAR (0..7_D)
DTCT is the transfer register (read only) for a 16-bit DTC Table entry. The Read process
is controlled by the MAR (Memory Address Register). The 5 LSBs (= Bit 4..0) of the MAR
register select the memory/table that will be accessed; to select the DTC Table, bit field
MAR(4:0) must be set to 05_H. Bit 5 of MAR starts the transfer and is automatically
cleared after execution.
Table 7-5 WAR Register Mapping for DTC Table access
Bit
15
14
13
12
11
10
9
8
Unused(11:4)
Bit
7
6
5
Unused(3:0)
4
3
2
1
0
Core
EntrySel(3:0)
Core
EntrySel(3:0)
Selects the core (upstream/downstream) for access of the DBA
Threshold Crossing Indication entries:
0
Upstream Core
1
Downstream Core
Selects one of the 8 DBA Threshold Crossing Indication Entries.
Data Sheet
235
2001-12-17