PXF4336 Datasheet, PDF (343/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

Register 104 PLL2CONF
PLL2 Configuration Register
ABM-P
PXF 4336 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
PLL2CONF D8_H
Written and Read by CPU
Bit
15
14
13
12
11
Locked2 unused Dev1En BYPAS PU2
2
S2
10
RES2
Bit
7
6
5
4
3
2
M2(1:0)
N2(5:0)
9
8
M2(3:2)
1
0
DPLL2 generates a clock that is an alternative clock source for the ERC unit. The
DPLL2 is fed by clock input signal ‘SYSCLK’. Signal ‘IOPCLKSEL’ determines the clock
source of the ERC unit. Section 3.2.7 “Clocking System” on Page 55 provides the
details.
Locked2
DPLL2 Locked
(read only)
1
DPLL2 is locked based on the current parameter
setting.
0
DPLL2 is in transient status.
Div1En2
Division Factor 1 Enable for DPLL2
This bit enables the additional divide by 2 factor subsequent to the
DPLL2 output.
0
Division Factor 1 disabled.
1
Division Factor 1 enabled.
Data Sheet
343
2001-12-17