PXF4336 Datasheet, PDF (111/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

ABM-P
PXF 4336 V1.1
Functional Description
3.5.2.1 Processor
The ABM-P includes a general purpose RISC processor on-chip, called IOP. The IOP is
responsible for ABR explicit rate calculation and the implementation of VS/VD behavior.
The basic parameters for the ABM-P IOP are:
• 24 bit instruction width
• Program/Code RAM Interface (24 bit data, 13 bit address bus)
• Data RAM Interface (16 bit, 16 bit address bus) shared by context RAM, extended
context RAM and variable RAM (upper Cache RAM page)
• 16 Ports mapped into register file
• 4 tasks with 16 registers each
• 4 interrupt inputs managed by a separate interrupt controller
3.5.2.2 Message Interface
For communication between the ERC unit and the ABM-P core, a Message Interface is
implemented. It is designed to support both ABR and VBR (Rate Shaping) related
calculations in the IOP. Since standard VBR shaping is performed entirely in hardware,
the VBR related messages are currently unused and are not supported.
ERC
Unit
ABR
support
RM FIFO
Emit FIFO
RM_Cell_received (QID , first 24 bytes) ^ABM-P
Core
Emit (QID, Qlen, Tnow)
Rate_update_ABR (T)
ABR
support
RM_Cell_update (ER, CI, NI)
RM_Cell_insert (first 24 octets)
Figure 3-48 Message Interface between ERC Unit and ABM-P Core
Towards the ERC unit, the messages sent by the ABM-P core are buffered in two FIFO
queues: the RM FIFO and the Emit FIFO.
Data Sheet
111
2001-12-17