PXF4336 Datasheet, PDF (237/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

7.2.10 LCI Table Transfer Registers
ABM-P
PXF 4336 V1.1
Register Description
Internal Table 2: LCI Table Transfer Registers LCI0, LCI1, LCI2
These registers are used to access the internal Local Connection Identifier (LCI) table
containing 16384 entries (one entry serves for upstream and downstream direction).
Table 7-6 shows an overview of the registers involved.
Table 7-6 Registers for LCI Table Access
47
0
LCI RAM entry
15
0 15
0 15
0
LCI2
LCI1
LCI0
15
0 15
0 15
0
MASK2
MASK1
MASK0
RAM select:
15
0
MAR=00_H
LCI select:
15
0
WAR (0..16383_D)
LCI0, LCI1 and LCI2 are the transfer registers for one 48-bit LCI table entry. The LCI
value representing the table entry which needs to be read or written must be written to
the Word Address Register (WAR). The dedicated LCI table entry is read into the LCI0/
LCI1/LCI2 Registers or modified by the LCI0/LCI1/LCI2 Register values with a write
mechanism. The associated Mask Registers MASK0 to MASK2 allow a bit-wise masking
for Write operation (0 - unmasked, 1 - masked). In case of Read operation, the dedicated
LCI0/LCI1/LCI2 register bit will be overwritten by the respective LCI table entry bit value.
In case of Write operation, the dedicated LCI0/LCI1/LCI2 register bit will modify the
respective LCI table entry bit value.
The Read or Write process is controlled by the Memory Address Register (MAR). The 5
LSBs (= Bit 4..0) of the MAR select the memory/table that will be accessed; to select the
LCI table bit field MAR(4:0) must be set to 0. Bit 5 of the MAR starts the transfer and is
automatically cleared after execution.
Table 7-7 WAR Register Mapping for LCI Table Access
Bit
15
14
13
12
11
10
9
8
Unused(2:0)
LCISel(13:8)
Bit
7
6
5
4
3
2
1
0
LCISel(7:0)
LCISel(13:0)
Selects an LCI entry within the range (0..16383).
Data Sheet
237
2001-12-17