PXF4336 Datasheet, PDF (148/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

ABM-P
PXF 4336 V1.1
Operational Description
Definition of Necessary Traffic Classes
The ABM-P allows up to 16 traffic classes to be defined by Traffic Class Table RAM entry
via the registers TCT0 to TCT3 (see Page 244f). In this example, there are 3 traffic
classes:
• CBR (real-time) = traffic class 1
• GFR (non-real-time) = traffic class 2
• UBR (non-real-time) = traffic class 3
Assignment of the Queues to the Traffic Classes
Each queue must relate to a defined traffic class according to the Queue Configuration
Table RAM entry via the TCID(3:0) bits of the QCT table.
Assignment of the Queues (QIDs) to the Scheduler Blocks (SBIDs)
Every Scheduler Block (SB) possesses a certain number of queues depending on the
assignment by the user of the SBID(5:0) bits of register “QCT1” on Page 261. In the ex-
ample, every ADSL device has four data connections so that four queues per SB are
necessary. Each SB of the ABM-P has one real-time queue and an arbitrary number of
non-real-time queues. For SB 0..254, indicate that the first queue belongs to Traffic
Class 1, the 2nd and 3rd Queue to Traffic Class 2, and the 4th Queue to Traffic Class 3.
There are 1020 (1..1020) queues altogether for SB 0..254. The 256th SB must be able
to serve the 255 xDSL devices (255 SBs and appropriate queues). Thus, SB 255 has
255 x 2 = 510 non-real-time queues as every SB from 0..254 possesses two GFR non-
real-time queues (GFR has a guaranteed minimum rate; thus, each GFR queue needs
a per VC queueing). The 255 UBR queues of SBs 0..254 need only one UBR queue at
the 256th SB as UBR has no guaranteed minimum rate. As every SB has only one real-
time queue, the 255 real-time queues from SBs 0..254 flow into the one real-time queue
of SB 255. Therefore, SB 256 needs the assignment of 510 (GFR) + 1 (UBR) + 1 (CBR)
= 512 queues.
4.2.4 Normal Operation
In normal operation, no microprocessor interaction is necessary as the ABM-P chip does
all queueing and scheduling automatically. For maintenance purposes, periodically the
microprocessor could read out the counters for buffer overflow events. Some overflow
events may also be programmed as interrupts.
The only instance of permanent microprocessor interaction is operation of the dynamic
bandwidth allocation protocol. In this case, the microprocessor must permanently check
the fill thresholds of the upstream SBs and adjust their output rates accordingly.
In case of static bandwidth allocation, all rate adjustments are made only at connection
setup or teardown.
Data Sheet
148
2001-12-17