PXF4336 Datasheet, PDF (57/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

ABM-P
PXF 4336 V1.1
Functional Description
f₁ = f_in ⁄ (m + 1)
;
f₂
=
f_in
×
-ⁿ-----+-----¹---
m+1
Register PLL1CONF
15
Lockedi Div2Eni Div1Eni Bypassi PUi RESi
Mi(3:0)
0
Ni(5:0)
f_in
(1)
1
f₁
2..15 MHz
f₂
(1)
(1)
X
(n + 1)
X
1/2 X
1/2
(m + 1)
(0)
(0)
(0)
f_out
Figure 3-8 DPLL Structure
The division factor determined by m must be chosen such that intermediate frequency
f₁ is in the range 2..15 MHz based on the input frequency at signal ‘SYSCLK’.
The multiplication factor determined by n must be chosen such that intermediate
frequency f₂ is equal or twice the final value in case of DPLL2 and twice or four times the
final value in case of DPLL1.
Finally, the division by the two factors (f₁,f₂) may be enabled in case of DPLL2 and one
or two divisions by the two factors (f₁,f₂) may be enabled in case of DPLL1 to achieve the
final clock frequency.
When choosing the factors m and n, two conditions must be met:
• n=1..24: f₁ must be in a range of 5..15 MHz
n=25..63: f₁ must be in a range of 2..6 MHz
• f₂ must be in a range of 100 to 200 MHz
3.2.7.3 Programming Example
The following numbers are assumed for this example:
• ABM-P internal core clock: 52 MHz
• ABM-P ERC clock: 60 MHz
• Clock supply: 52 MHz at signal SYSCLK
Data Sheet
57
2001-12-17