PXF4336 Datasheet, PDF (213/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

ABM-P
PXF 4336 V1.1
Register Description
Register 15 UBufferOccNg/DBufferOccNg
Up-/Downstream Non-Guaranteed Buffer Occupation Registers
CPU Accessibility: Read only
Reset Value:
Offset Address:
Typical Usage:
0000_H
UBufferOccNg 22_H
Read by CPU
DBufferOccNg 23_H
Bit
15
14
13
12
11
10
9
8
UBufferOccNg/DBufferOccNg(17:10)
Bit
7
6
5
4
3
2
1
0
UBufferOccNg/DBufferOccNg(9:2)
•
UBufferOccNg(17:2) Upstream Non-Guaranteed Buffer Occupation Counter
DBufferOccNg(17:2) Downstream Non-Guaranteed Buffer Occupation Counter
These bit fields represent the most significant 16 bits of the
internal 18-bit wide counters reflecting the number of non-
guaranteed cells currently stored in the upstream/downstream
cell storage RAM.
The CPU determines the number of cells with a granularity of 4
by reading register UBufferOccNg/DBufferOccNg and left
shifting the value by 2:
fill_level(17:0):= (xBufferOccNg(17:2) << 2)
“Non-Guaranteed” cell count refers to cells, that are accepted
(stored) because of shared buffer availability although the
guaranteed minimum per queue buffer size is already occupied
by the specific queue.
The sum of all per queue guaranteed buffer sizes virtually
divides the global buffer space into a “guaranteed” part and a
“non-guaranteed” (shared) part.
Note: This counter function has been modified from ABM v1.1
since minimum per queue buffer reservation was
introduced in ABM-P v1.1.
In ABM v1.1 these counters represented the number
stored “non-real-time” cells belonging to traffic classes
with the real-time indication bit ’RTind’ cleared in the
traffic class table.
Data Sheet
213
2001-12-17