PXF4336 Datasheet, PDF (261/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

Register 44 QCT1
Queue Configuration Transfer Register 1
ABM-P
PXF 4336 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
QCT1
43_H
Written and Read by CPU to maintain the LCI table
Bit
15
14
13
12
11
10
9
8
DQac
RSall
VS/VD
en
ABR
dir
TCID(3:0)
Bit
7
6
5
4
3
2
1
0
QIDvalid
SBID(6:0)
DQac
Dummy Queue Action
This bit is a command bit that must always be set when a dummy
queue is activated or deactivated.
Note: Read access to this command bit will always return ’0’.
RSall
ReSchedule Always
This bit determines the queue scheduling process:
’0’
The queue is only scheduled/re-scheduled with its
specific rate while the queue is not empty (normal
operation).
Data Sheet
261
2001-12-17