PXF4336 Datasheet, PDF (217/425 Pages) Infineon Technologies AG – ABM Premium ATM Buf fer Manager

ABM-P
PXF 4336 V1.1
Register Description
Register 18 UMIC/DMIC
Upstream/Downstream Minimum Occupation Capture Registers
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read only, self-clearing on Read
FFFF_H
(modified by chip logic immediately after reset)
UMIC
28_H
Read by CPU
DMIC
29_H
Bit
15
14
13
12
11
10
9
8
UMIC/DMIC(17:10)
Bit
7
6
5
4
3
2
1
0
UMIC/DMIC(9:2)
UMIC(17:2)
DMIC(17:2)
Upstream Minimum Occupation Capture Counter
Downstream Minimum Occupation Capture Counter
These bit fields represent the most significant 16 bits of the internal
18-bit wide counters reflecting the absolute minimum number of
cells stored in the respective external cell buffer since the last Read
access (minimum cell filling level within measurement interval).
The CPU determines the minimum number of cells with a
granularity of 4 by reading register UMIC/DMIC and left shifting the
value by 2:
min_level(17:0):= (xMIC(17:2) << 2)
The counter value is automatically cleared to 0000_H after Read.
Note: The reset value is modified by chip logic immediately after
reset or clearing read and thus shall not be included in
register reset value test programs.
Data Sheet
217
2001-12-17