TC290 Datasheet, PDF (438/476 Pages) Infineon Technologies AG – 32-Bit Single-Chip Micocontroller

3.32
EBU Timings
TC290 / TC297 / TC298 / TC299 BB-Step
Electrical SpecificationEBU Timings
3.32.1 BFCLKO Output Clock Timing
V_SS = 0 V;V_DD = 1.3 V ± 5%; V_DDEBU = 2.5 V ± 5% and 3.3 V ± 5%,;
C_L = 35 pF
Table 3-95 BFCLK0 Output Clock Timing Parameters¹⁾
Parameter
Symbol
Values
Unit Note /
Min.
Typ. Max.
Test Conditi
on
BFCLKO clock period
t_BFCLKO CC
13.33²⁾ –
–
ns –
BFCLKO high time
t₅
CC
3
–
–
ns –
BFCLKO low time
t₆
CC
3
–
–
ns –
BFCLKO rise time
t₇
CC
–
–
3
ns –
BFCLKO fall time
t_{8 CC}
–
–
3
BFCLKO duty cycle t₅/(t₅ + t₆)³⁾
DC
35
50
55
1) Not subject to production test, verified by design/characterization.
ns –
%
–
2) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter parameters.
3) The PLL jitter is not included in this parameter. If the BFCLKO frequency is equal to f_CPU, the K divider has to be regarded.
t_BFCLKO
BFCLKO 0.5 V_DDP05
t₅
t₆
t₈
Figure 3-30 BFCLKO Output Clock Timing
0.9 V_DD
t₇
0.1 V_DD
MCT04883_mod
3.32.2 EBU Asynchronous Timings
V_SS = 0 V;V_DD = 1.3 V ± 5%; V_DDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
C_L = 35 pF for address/data; C_L = 40pF for the control lines.
For each timing, the accumulated PLL jitter of the programed duration in number of clock periods must be added
separately. Operating conditions apply and C_L = 35 pF.
Table 3-96 Common Asynchronous Timings
Parameter
Symbol
Min.
AD(31:0) output delay to ADV# t₁₃ CC
-5.5
rising edge, multiplexed read /
write
AD(31:0) output delay to ADV# t₁₄ CC
-5.5
rising edge, multiplexed read /
write
Values
Typ.
-
Max.
2
Unit Note / Test Condition
ns
-
2
ns
Data Sheet
3-432
V 1.1 2015-05
TC290/TC297/TC298/TC299 BB-Step Data Sheet downloaded by saravanakumar maniyam (larsen and Toubro limited) at 08 Sep 2015 08:06