TC290 Datasheet, PDF (412/476 Pages) Infineon Technologies AG – 32-Bit Single-Chip Micocontroller

TC290 / TC297 / TC298 / TC299 BB-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
Table 3-70 Master Mode timing MPss output pads (cont’d)
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
Typ.
Max.
MRST setup to SCLK latching t₅₂ SR
50 ⁴⁾⁵⁾
-
-
ns
C_L=25pF
edge ⁴⁾
MRST hold from SCLK latching t₅₃ SR
-6 ⁴⁾⁵⁾
-
-
ns
C_L=25pF
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of T_MAX = 1 / f_MAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-71 Master Mode timing MPsm output pads
Parameter
Symbol
Values
Unit Note / Test Condition
SCLKO clock period ¹⁾
Deviation from the ideal duty
cycle ^{2) 3)}
MTSR delay from SCLKO
shifting edge
t₅₀ CC
t₅₀₀ CC
t₅₁ CC
Min.
200
-5
-19
Typ.
-
-
-
Max.
-
ns
9+0.06 * ns
C_L
19
ns
C_L=50pF
0 < C_L < 200pF
C_L=50pF
SLSOn deviation from the ideal t₅₁₀ CC
-19
-
programmed position
17
ns
C_L=50pF
MRST setup to SCLK latching t₅₂ SR
100 ⁴⁾⁵⁾ -
-
ns
C_L=50pF
edge ⁴⁾
MRST hold from SCLK latching t₅₃ SR
-13 ⁴⁾⁵⁾
-
-
ns
C_L=50pF
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of T_MAX = 1 / f_MAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-72 Master Mode timing MPRm/MP+m/MPm/LPm output pads
Parameter
Symbol
Values
Unit
SCLKO clock period ¹⁾
Deviation from the ideal duty
cycle ^{2) 3)}
t₅₀ CC
t₅₀₀ CC
Min.
400
-6-0.07 *
C_L
Typ.
-
-
Max.
-
ns
6+0.095 * ns
C_L
Note / Test Condition
C_L=50pF
0 < C_L < 200pF
Data Sheet
3-406
V 1.1 2015-05
TC290/TC297/TC298/TC299 BB-Step Data Sheet downloaded by saravanakumar maniyam (larsen and Toubro limited) at 08 Sep 2015 08:06