TC290 Datasheet, PDF (374/476 Pages) Infineon Technologies AG – 32-Bit Single-Chip Micocontroller

3.14
Power-up and Power-down
TC290 / TC297 / TC298 / TC299 BB-Step
Electrical SpecificationPower-up and Power-down
3.14.1 External Supply Mode
5 V & 1.3 V supplies are externally supplied. 3.3V is generated internally by EVR33.
• External supplies VEXT and VDD may ramp-up or ramp-down independent of each other with regards to start,
rise and fall time(s). Voltage Ramp-up from a residual threshold (Eg : up to 1 V) should also lead to a normal
startup of the device.
• The rate at which current is drawn from the external regulator (dIEXT /dt or dIDD /dt) is limited in the Start-up
phase to a maximum of 50 mA/100 us.
• PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
• PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary
reset thresholds.
• PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus
propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among
the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The
PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the
basic supply and clock infrastructure is available.
• The power sequence as shown in Figure 3-4 is enumerated below
– T1 refers to the point in time when basic supply and clock infrastructure is available as the external supplies
ramp up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of
EVR33 regulator is initiated.
– T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR33 regulator
has ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST rising edge.
Firmware execution is initiated.
– T3 refers to the point in time when Firmware execution is completed. User code execution starts with a
default frequency of 100 MHz.
– T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or
generated supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset
thresholds.
Please note that there is no special requirements for PORST slew rates.
Data Sheet
3-368
V 1.1 2015-05
TC290/TC297/TC298/TC299 BB-Step Data Sheet downloaded by saravanakumar maniyam (larsen and Toubro limited) at 08 Sep 2015 08:06