English
Language : 

TC290 Datasheet, PDF (400/476 Pages) Infineon Technologies AG – 32-Bit Single-Chip Micocontroller
TC290 / TC297 / TC298 / TC299 BB-Step
Electrical SpecificationASCLIN SPI Master Timing
3.23
ASCLIN SPI Master Timing
This section defines the timings for the ASCLIN in the TC290 / TC297 / TC298 / TC299, for 3.3V power supply,
Medium Performance pads, strong sharp edge (MPss), CL=25pF.
Note: Pad asymmetry is already included in the following timings.
Table 3-51 Master Mode MP+ss/MPRss output pads
Parameter
Symbol
Values
ASCLKO clock period 1)
t50 CC
Deviation from ideal duty cycle t500 CC
2)
Min.
40
-5
Typ.
-
-
Max.
-
5
Unit Note / Test Condition
ns
CL=25pF
ns
0 < CL < 50pF
MTSR delay from ASCLKO t51 CC
-12
-
shifting edge
12
ns
CL=25pF
ASLSOn delay from the first t510 CC
0
-
ASCLKO edge
60
ns
CL=25pF; pad used =
LPm
MRST setup to ASCLKO
t52 SR
50
-
-
ns
CL=25pF
latching edge
MRST hold from ASCLKO
t53 SR
-5
-
-
ns
CL=25pF
latching edge
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-52 Master Mode MP+sm/MPRsm output pads
Parameter
Symbol
Values
ASCLKO clock period 1)
t50 CC
Deviation from ideal duty cycle t500 CC
2)
Min.
100
-3
Typ.
-
-
Max.
-
7
Unit Note / Test Condition
ns
CL=50pF
ns
0 < CL < 200pF
MTSR delay from ASCLKO t51 CC
-17
-
shifting edge
17
ns
CL=50pF
ASLSOn delay from the first t510 CC
0
-
ASCLKO edge
60
ns
CL=50pF; pad used =
LPm
MRST setup to ASCLKO
t52 SR
85
-
-
ns
CL=50pF
latching edge
MRST hold from ASCLKO
t53 SR
-5
-
-
ns
CL=50pF
latching edge
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
3-394
V 1.1 2015-05
TC290/TC297/TC298/TC299 BB-Step Data Sheet downloaded by saravanakumar maniyam (larsen and Toubro limited) at 08 Sep 2015 08:06