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TC290 Datasheet, PDF (423/476 Pages) Infineon Technologies AG – 32-Bit Single-Chip Micocontroller
TC290 / TC297 / TC298 / TC299 BB-Step
Electrical SpecificationMSC Timing 3.3 V Operation
Table 3-80 MPss clock/data (LVDS pads in CMOS mode, option EN01)
Parameter
Symbol
Values
Unit Note / Test Condition
FCLPx clock period 1)
t40 CC
Deviation from ideal duty cycle t400 CC
4) 5)
SOPx output delay 6)
ENx output delay 6)
t44 CC
t45 CC
Min.
Typ.
2 * TA 2) 3) -
-5
-
-7
-
-9
-
-4
-
-7
-
0
-
Max.
-
ns
7+0.07 * ns
CL
12
ns
12
ns
26
ns
17
ns
56
ns
MPss; CL=50pF
MPss; 0 < CL < 100pF
MPss; CL=50pF
MP+ss/MPRss;
CL=50pF
MP+sm/MPRsm;
CL=50pF
MPss; CL=50pF
MPsm; CL=50pF;
except pin P13.0
0
-
58
ns
MPsm; CL=50pF; pin
P13.0
4
-
77
ns
MPm/MP+m/MPRm;
CL=50pF
-19
-
8
ns
MP+ss/MPRss;
CL=0pF
-7
-
19
ns
MP+sm/MPRsm;
CL=0pF
-17
-
8
ns
MPss; CL=0pF
-2
-
38
ns
MPsm; CL=0pF
-4
-
41
ns
MP+m/MPm/MPRm;
CL=0pF
SDI bit time
t46 CC
8 * tMSC -
-
ns
Upstream Timing
SDI rise time 7)
t48 SR
-
-
200
ns
Upstream Timing
SDI fall time 7)
t49 SR
-
-
200
ns
Upstream Timing
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.
2) TAmin = TMAX. When TMAX = 100 MHz,t40 = 20 ns
3) FCLP signal high and low can be minimum 1 * TMSC.
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
6) From FCLP rising edge.
7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in
the middle of the bit are not violated.
Data Sheet
3-417
V 1.1 2015-05
TC290/TC297/TC298/TC299 BB-Step Data Sheet downloaded by saravanakumar maniyam (larsen and Toubro limited) at 08 Sep 2015 08:06