TC290 Datasheet, PDF (398/476 Pages) Infineon Technologies AG – 32-Bit Single-Chip Micocontroller

TC290 / TC297 / TC298 / TC299 BB-Step
Electrical SpecificationASCLIN SPI Master Timing
Table 3-49 Master Mode medium output pads
Parameter
Symbol
Values
Unit Note / Test Condition
ASCLKO clock period ¹⁾
t₅₀ CC
Deviation from ideal duty cycle t₅₀₀ CC
2)
MTSR delay from ASCLKO
shifting edge
t₅₁ CC
Min.
200
-8
-20
Typ.
-
-
-
Max.
-
ns
4+0.06 * ns
C_L
18.5
ns
C_L=50pF
0 < C_L < 200pF
C_L=50pF
ASLSOn delay from the first t₅₁₀ CC
-20
-
ASCLKO edge
20
ns
C_L=50pF
MRST setup to ASCLKO
t₅₂ SR
70
-
-
ns
C_L=50pF
latching edge
MRST hold from ASCLKO
t₅₃ SR
-10
-
-
ns
C_L=50pF
latching edge
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of T_MAX = 1 / f_MAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-50 Master Mode weak output pads
Parameter
Symbol
Values
Unit Note / Test Condition
ASCLKO clock period ¹⁾
t₅₀ CC
Deviation from ideal duty cycle t₅₀₀ CC
2)
MTSR delay from ASCLKO
shifting edge
t₅₁ CC
Min.
1000
-30
-75
Typ.
-
-
-
Max.
-
ns
30+0.15 * ns
C_L
75
ns
C_L=50pF
0 < C_L < 200pF
C_L=50pF
ASLSOn delay from the first t₅₁₀ CC
-65
-
ASCLKO edge
65
ns
C_L=50pF
MRST setup to ASCLKO
t₅₂ SR
510
-
-
ns
C_L=50pF
latching edge
MRST hold from ASCLKO
t₅₃ SR
-50
-
-
ns
C_L=50pF
latching edge
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of T_MAX = 1 / f_MAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Data Sheet
3-392
V 1.1 2015-05
TC290/TC297/TC298/TC299 BB-Step Data Sheet downloaded by saravanakumar maniyam (larsen and Toubro limited) at 08 Sep 2015 08:06