TC290 Datasheet, PDF (316/476 Pages) Infineon Technologies AG – 32-Bit Single-Chip Micocontroller

TC290 / TC297 / TC298 / TC299 BB-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Column “Name”:
Symbolic name of the pad.
The functions mapped on GPIO pads “Px.y” are described in the User’s Manual chapter ”General Purpose I/O
Ports and Peripheral I/O LInes (Ports)”
Column “Type”:
LP = Pad class LP (5V/3.3V, Class LP parameters for digital input / output and class D parameters for analog input
function)
MP = Pad class MP (5V/3.3V)
MP+ = Pad class MP+ (5V/3.3V)
MPR = Pad class MPR (5V/3.3V)
A2 = Pad class A2 (3.3V)
LVDSM = Pad class LVDSM (5V/3.3V)
LVDSH = Pad class LVDSH (3.3V)
S = Pad class S (Class S parameters for digital input and class D parameters for analog input function)
D = Pad class D (VADC / DSADC)
PU = with pull-up device connected during reset (PORST = 0)
PU1 = with pull-up device connected during reset (PORST = 0)^{1) 2) 3)}
PD = with pull-down device connected during reset (PORST = 0)
PD1 = with pull-down device connected during reset (PORST = 0)^{1) 2) 3)}
PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode
OD = open drain during reset (PORST = 0)
HighZ = tri-state during reset (PORST = 0)
PORST = PORST input pad
XTAL1 = XTAL1 input pad
XTAL2 = XTAL2 input pad
VGATE1P = VGATE1P
VGATE3P = VGATE3P
Vx = Supply
NC = These pins are reserved for future extensions and shall not be connected externally
NC1 = These pins are not connected on package level and will not be used for future extensions
NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details
pls. see Pin/Ball description of this pin.
Column “X” / “Y”:
Pad opening center coordinates
2.4.1 Pad Openings
Two different pad openings are used:
1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a
weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”,
“General Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”.
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups are active at GPIOs (Px.y) pins during
and after reset. Exceptions are P33.8 (HighZ), P40.x (default configuration during and after reset: analog inputs, port input
funtion disabled), ESR0, P21.6 / P21.7 (port pins overlayed with JTAG functionality).
3) If HWCFG[6] is connected to ground, port pins are predominantly in HighZ during and after reset. Exceptions are P33.8
(HighZ), P40.x (default configuration during and after reset: analog inputs, port input funtion disabled), ESR0, P21.6 / P21.7
(port pins overlayed with JTAG functionality).
Data Sheet
2-310
V 1.1 2015-05
TC290/TC297/TC298/TC299 BB-Step Data Sheet downloaded by saravanakumar maniyam (larsen and Toubro limited) at 08 Sep 2015 08:06