TC290 Datasheet, PDF (408/476 Pages) Infineon Technologies AG – 32-Bit Single-Chip Micocontroller

TC290 / TC297 / TC298 / TC299 BB-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of T_MAX = 1 / f_MAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.
Table 3-66 Slave mode timing
Parameter
Symbol
SCLK clock period
SCLK duty cycle
MTSR setup to SCLK latching
edge
t₅₄ SR
t_55/t54 SR
t₅₆ SR
MTSR hold from SCLK latching t₅₇ SR
edge
SLSI setup to first SCLK shift t₅₈ SR
edge
SLSI hold from last SCLK
latching edge
t₅₉ SR
MRST delay from SCLK shift t₆₀ CC
edge
Min.
4 x T_MAX
40
4 ¹⁾
5 ¹⁾
5 ¹⁾
3.5 ¹⁾
6 ¹⁾
9 ¹⁾
5 ¹⁾
4 ¹⁾
8 ¹⁾
6
3 ¹⁾
4 ¹⁾
8 ¹⁾
10
Values
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
-
60
-
-
-
-
-
-
-
-
-
-
-
-
-
70
9
-
50
5
-
30
40
-
300
10
-
70
10
-
55
5
-
30
40
-
300
SLSI to valid data on MRST t₆₁ SR
-
-
5
1) Except pin P15.1.
Unit Note / Test Condition
ns
%
ns
Hystheresis Inactive
ns
Input Level AL
ns
Input Level TTL
ns
Hystheresis Inactive
ns
Input Level AL
ns
Input Level TTL
ns
Hystheresis Inactive
ns
Input Level AL
ns
Input Level TTL
ns
Only for pin 15.1, AL
ns
Hystheresis Inactive
ns
Input Level AL
ns
Input Level TTL
ns
MP+m/MPRm;
C_L=50pF
ns
MP+sm/MPRsm;
C_L=50pF
ns
MP+ss/MPRss;
C_L=25pF
ns
MP+w/MPRw;
C_L=50pF
ns
MPm/LPm; C_L=50pF
ns
MPsm; C_L=50pF
ns
MPss; C_L=25pF
ns
MPw/LPw; C_L=50pF
ns
Data Sheet
3-402
V 1.1 2015-05
TC290/TC297/TC298/TC299 BB-Step Data Sheet downloaded by saravanakumar maniyam (larsen and Toubro limited) at 08 Sep 2015 08:06