TC290 Datasheet, PDF (410/476 Pages) Infineon Technologies AG – 32-Bit Single-Chip Micocontroller

TC290 / TC297 / TC298 / TC299 BB-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
– medium edge (LP/MPm), C_L=50pF
– weak edge (MPw), C_L=50pF
Table 3-67 Master Mode Timing, LVDSM output pads for data and clock
Parameter
Symbol
Values
Unit Note / Test Condition
SCLKO clock period ¹⁾
Deviation from the ideal duty
cycle ^{2) 3)}
t₅₀ CC
t₅₀₀ CC
Min.
20
-2
Typ.
-
-
Max.
-
ns
C_L=25pF
2
ns
C_L=25pF
MTSR delay from SCLKO
t₅₁ CC
-5
-
shifting edge
5
ns
C_L=25pF
SLSOn deviation from the ideal t₅₁₀ CC
-2
-
programmed position
-9
-
-7
-
-2
-
MRST setup to SCLK latching t₅₂ SR
20
-
edge ⁴⁾
55
ns
C_L=25pF; MPsm
12
ns
C_L=25pF; MPss
12
ns
MP+ss; C_L=25pF
26
ns
MP+sm; C_L=25pF
-
ns
C_L=25pF; LVDSM 5V
output and LVDSH
3.3V input
MRST hold from SCLK latching t₅₃ SR
-6
-
-
ns
C_L=25pF; LVDSM 5V
edge
output and LVDSH
3.3V input
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted using the bit fields ECONz.A, B and C with the finest granularity of T_MAX = 1 / f_MAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.
Table 3-68 Master Mode MP+ss/MPRss output pads
Parameter
Symbol
Values
Unit Note / Test Condition
SCLKO clock period ¹⁾
Deviation from the ideal duty
cycle ^{2) 3)}
t₅₀ CC
t₅₀₀ CC
Min.
40
-5
Typ.
-
-
Max.
-
5
ns
C_L=25pF
ns
0 < C_L < 50pF
MTSR delay from SCLKO
t₅₁ CC
-12
-
shifting edge
12
ns
C_L=25pF
SLSOn deviation from the ideal t₅₁₀ CC
-12
-
programmed position
12
ns
C_L=25pF
MRST setup to SCLK latching t₅₂ SR
50 ⁴⁾⁵⁾
-
-
ns
C_L=25pF
edge ⁴⁾
MRST hold from SCLK latching t₅₃ SR
-5 ⁴⁾⁵⁾
-
-
ns
C_L=25pF
edge
1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has
to be taken into account.
Data Sheet
3-404
V 1.1 2015-05
TC290/TC297/TC298/TC299 BB-Step Data Sheet downloaded by saravanakumar maniyam (larsen and Toubro limited) at 08 Sep 2015 08:06