TC290 Datasheet, PDF (403/476 Pages) Infineon Technologies AG – 32-Bit Single-Chip Micocontroller

TC290 / TC297 / TC298 / TC299 BB-Step
Electrical SpecificationASCLIN SPI Master Timing
Table 3-57 Master Mode A2ss output pads (cont’d)
Parameter
Symbol
Values
Unit Note / Test Condition
Min.
Typ.
Max.
MRST setup to ASCLKO
t₅₂ SR
17
-
-
ns
C_L=50pF
latching edge
MRST hold from ASCLKO
t₅₃ SR
0
-
-
ns
C_L=50pF
latching edge
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of T_MAX = 1 / f_MAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
Table 3-58 Master Mode A2sm output pads
Parameter
Symbol
ASCLKO clock period ¹⁾
t₅₀ CC
Deviation from ideal duty cycle t₅₀₀ CC
2)
Min.
40
-4
Values
Typ.
-
-
Max.
-
4
Unit Note / Test Condition
ns
C_L=50pF
ns
C_L=50pF
MTSR delay from ASCLKO t₅₁ CC
-8
-
shifting edge
6
ns
C_L=50pF
ASLSOn delay from the first t₅₁₀ CC
-8
-
ASCLKO edge
9
ns
C_L=50pF
MRST setup to ASCLKO
t₅₂ SR
26
-
-
ns
C_L=50pF
latching edge
MRST hold from ASCLKO
t₅₃ SR
0
-
-
ns
C_L=50pF
latching edge
1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be
adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of T_MAX = 1 / f_MAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the
opposite.
ASCLKO
MTSR
MRST
ASLSO
t₅₀
t₅₁
t₅₀₀
t₅₂
t₅₃
Data valid
t₅₁₀
Figure 3-17 ASCLIN SPI Master Timing
t₅₁
Data valid
ASCLIN_TmgMM.vsd
Data Sheet
3-397
V 1.1 2015-05
TC290/TC297/TC298/TC299 BB-Step Data Sheet downloaded by saravanakumar maniyam (larsen and Toubro limited) at 08 Sep 2015 08:06