TC290 Datasheet, PDF (409/476 Pages) Infineon Technologies AG – 32-Bit Single-Chip Micocontroller

TC290 / TC297 / TC298 / TC299 BB-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode
SCLK¹⁾²⁾
t₅₀
t₅₀₀
t₅₁
0.5 VEXT/FLEX
SAMPLING POINT
MTSR¹⁾
MRST¹⁾
SLSOn²⁾
t52
t₅₃
Data valid
t₅₁₀
0.5 VEXT/FLEX
Data valid
0.5 VEXT/FLEX
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay).
2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0.
QSPI_TmgMM.vsd
Figure 3-18 Master Mode Timing
SCLKI¹⁾
MTSR¹⁾
MRST¹⁾
SLSI
t₅₄
First shift
SCLK edge
First latching
SCLK edge
t₅₅
t₅₅
t₅₆
t₅₇
Data
valid
t₆₀
t₆₀
t58
t₆₁
Last latching
SCLK edge
0.5 VEXT/FLEX
t₅₆
t₅₇
Data
valid
0.5 VEXT/FLEX
t₅₉
1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0. _{QSPI_TmgSM.vsd}
Figure 3-19 Slave Mode Timing
3.25
QSPI Timings, Master and Slave Mode
This section defines the timings for the QSPI in the TC290 / TC297 / TC298 / TC299, for 3.3V pad power supply.
It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings:
• LVDSM output pads,LVDSH input pad, master mode, C_L=25pF
• Medium Performance Plus Pads (MP+):
– strong sharp edge (MP+ss), C_L=25pF
– strong medium edge (MP+sm), C_L=50pF
– medium edge (MP+m), C_L=50pF
– weak edge (MP+w), C_L=50pF
• Medium Performance Pads (MP):
– strong sharp edge (MPss), C_L=25pF
– strong medium edge (MPsm), C_L=50pF
• Medium and Low Performance Pads (MP/LP), the identical output strength settings:
Data Sheet
3-403
V 1.1 2015-05
TC290/TC297/TC298/TC299 BB-Step Data Sheet downloaded by saravanakumar maniyam (larsen and Toubro limited) at 08 Sep 2015 08:06