TC290 Datasheet, PDF (416/476 Pages) Infineon Technologies AG – 32-Bit Single-Chip Micocontroller

TC290 / TC297 / TC298 / TC299 BB-Step
3.26
MSC Timing 5 V Operation
Electrical SpecificationMSC Timing 5 V Operation
The following section defines the timings for 5V pad power supply.
Note: Pad asymmetry is already included in the following timings.
Note: Load for LVDS pads are defined as differential loads in the following timings.
Table 3-75 LVDS clock/data (LVDS pads in LVDS mode)
Parameter
Symbol
FCLPx clock period ¹⁾
t₄₀ CC
Deviation from ideal duty cycle t₄₀₀ CC
4) 5)
Values
Min.
Typ.
2 * T_A ^{2) 3)} -
-1
-
Max.
-
1
Unit Note / Test Condition
ns
LVDSM; C_L=50pF
ns
LVDSM; 0 < C_L < 50pF
SOPx output delay ⁶⁾
t₄₄ CC
-3
-
4
ns
LVDSM; C_L=50pF;
option EN01
-4
-
4.5
ns
LVDSM; C_L=50pF;
option EN01D
ENx output delay ⁶⁾
t₄₅ CC
-4
-
5
ns
MP+ss/MPRss; option
EN01; C_L=25pF
-3.5
-
7
ns
MP+ss/MPRss; option
EN01; C_L=50pF
-3
-
11
ns
MP+sm/MPRsm;
option EN01D;
C_L=50pF
-2.5
-
9
ns
MP+ss/MPRss; option
EN23; C_L=25pF
-2.5
-
10
ns
MP+ss/MPRss; option
EN23; C_L=50pF
-3
-
11
ns
MPss; option EN01;
C_L=50pF
-7
-
3
ns
MP+ss/MPRss; option
EN01; C_L=0pF
-5
-
3
ns
MP+sm/MPRsm;
option EN01D; C_L=0pF
-4
-
6
ns
MP+ss/MPRss; option
EN23; C_L=0pF
-7
-
4
ns
MPss; option EN01;
C_L=0pF
SDI bit time
t₄₆ CC
8 * t_MSC -
-
ns
Upstream Timing
SDI rise time ⁷⁾
t₄₈ SR
-
-
200
ns
Upstream Timing
SDI fall time ⁷⁾
t₄₉ SR
-
-
200
ns
Upstream Timing
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * T_A.
2) T_A depends on the clock source selected for baud rate generation in the ABRA block of the MSC.
3) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.
Data Sheet
3-410
V 1.1 2015-05
TC290/TC297/TC298/TC299 BB-Step Data Sheet downloaded by saravanakumar maniyam (larsen and Toubro limited) at 08 Sep 2015 08:06