MC9S12XD256CAL Datasheet, PDF (948/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
Table 23-47. PERH Field Descriptions
Field
Description
7–0
Pull Device Enable Port H
PERH[7:0] 0 Pull-up or pull-down device is disabled.
1 Either a pull-up or pull-down device is enabled.
23.0.5.51 Port H Polarity Select Register (PPSH)
R
W
Reset
7
PPSH7
0
6
PPSH6
5
PPSH5
4
PPSH4
3
PPSH3
2
PPSH2
0
0
0
0
0
Figure 23-53. Port H Polarity Select Register (PPSH)
1
PPSH1
0
0
PPSH0
0
Read: Anytime.
Write: Anytime.
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting
a pull-up or pull-down device if enabled.
Table 23-48. PPSH Field Descriptions
Field
Description
7–0
PPSH[7:0]
Polarity Select Port H
0 Falling edge on the associated port H pin sets the associated flag bit in the PIFH register.
A pull-up device is connected to the associated port H pin, if enabled by the associated bit in register PERH
and if the port is used as input.
1 Rising edge on the associated port H pin sets the associated flag bit in the PIFH register.
A pull-down device is connected to the associated port H pin, if enabled by the associated bit in register PERH
and if the port is used as input.
23.0.5.52 Port H Interrupt Enable Register (PIEH)
R
W
Reset
7
PIEH7
0
6
PIEH6
5
PIEH5
4
PIEH4
3
PIEH3
2
PIEH2
0
0
0
0
0
Figure 23-54. Port H Interrupt Enable Register (PIEH)
1
PIEH1
0
0
PIEH0
0
Read: Anytime.
Write: Anytime.
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with
Port H.
MC9S12XDP512 Data Sheet, Rev. 2.21
950
Freescale Semiconductor