MC9S12XD256CAL Datasheet, PDF (935/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Table 23-30. PPSS Field Descriptions
Field
Description
7–0
PPSS[7:0]
Pull Select Port S
0 A pull-up device is connected to the associated port S pin, if enabled by the associated bit in register PERS
and if the port is used as input or as wired-OR output.
1 A pull-down device is connected to the associated port S pin, if enabled by the associated bit in register PERS
and if the port is used as input.
23.0.5.29 Port S Wired-OR Mode Register (WOMS)
7
R
WOMS7
W
6
WOMS6
5
WOMS5
4
WOMS4
3
WOMS3
2
WOMS2
1
WOMS1
0
WOMS0
Reset
0
0
0
0
0
0
0
0
Figure 23-31. Port S Wired-OR Mode Register (WOMS)
Read: Anytime.
Write: Anytime.
This register configures the output pins as wired-OR. If enabled the output is driven active low only
(open-drain). A logic level of “1” is not driven. It applies also to the SPI and SCI outputs and allows
a multipoint connection of several serial modules. These bits have no influence on pins used as
inputs.
Table 23-31. WOMS Field Descriptions
Field
Description
7–0
Wired-OR Mode Port S
WOMS[7:0] 0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.