MC9S12XD256CAL Datasheet, PDF(887/1348 Page) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

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MC9S12XD256CAL Datasheet, PDF (887/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

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Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

Table 22-70. Expanded Bus Pin Functions versus Operating Modes (continued)

Single-Chip Modes

Pin

Normal

Special

Single-Chip

Single-Chip

Normal

Expanded

Expanded Modes

Emulation

Single-Chip

Emulation

Expanded

PE6

GPIO

GPIO

GPIO

TAGHI

TAGHI

PE5

GPIO

GPIO

RE

TAGLO

TAGLO

PE4

GPIO

or

ECLK

ECLK

or

GPIO

ECLK

or

GPIO

ECLK

ECLK

PE3

GPIO

GPIO

LDS

or

GPIO

LSTRB

LSTRB

PE2

GPIO

GPIO

WE

R/W

R/W

PJ5

GPIO

GPIO

GPIO

or

CS2

GPIO

GPIO

or

CS2

PJ4

GPIO

GPIO

GPIO

or

CS0 (1)

GPIO

GPIO

or

CS0 (1)

PJ2

GPIO

GPIO

GPIO

or

CS1

GPIO

GPIO

or

CS1

PJ0

GPIO

GPIO

GPIO

or

CS3

GPIO

GPIO

or

CS3

1 Depending on ROMON bit. Refer to Device Guide, S12X_EBI section and S12X_MMC section for details.

Special

Test

GPIO

GPIO

ECLK

or

GPIO

LSTRB

R/W

GPIO

or

CS2

GPIO

or

CS0

GPIO

or

CS1

GPIO

or

CS3

22.4.5 Low-Power Options

22.4.5.1 Run Mode

No low-power options exist for this module in run mode.

22.4.5.2 Wait Mode

No low-power options exist for this module in wait mode.

22.4.5.3 Stop Mode

All clocks are stopped. There are asynchronous paths to generate interrupts from stop on port P, H, and J.

22.5 Initialization and Application Information

â¢ It is not recommended to write PORTx and DDRx in a word access. When changing the register

pins from inputs to outputs, the data may have extra transitions during the write access. Initialize

the port data register before enabling the outputs.

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

889

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