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MC9S12XD256CAL Datasheet, PDF (144/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG). | |||
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
Table 4-18. ATDSTAT0 Field Descriptions (continued)
Field
4
FIFOR
3:0
CC[3:0}
Description
FIFO Over Run Flag â This bit indicates that a result register has been written to before its associated
conversion complete ï¬ag (CCF) has been cleared. This ï¬ag is most useful when using the FIFO mode because
the ï¬ag potentially indicates that result registers are out of sync with the input channels. However, it is also
practical for non-FIFO modes, and indicates that a result register has been over written before it has been read
(i.e., the old data has been lost). This ï¬ag is cleared when one of the following occurs:
⢠Write â1â to FIFOR
⢠Start a new conversion sequence (write to ATDCTL5 or external trigger)
0 No over run has occurred
1 Overrun condition exists (result register has been written while associated CCFx ï¬ag remained set)
Conversion Counter â These 4 read-only bits are the binary value of the conversion counter. The conversion
counter points to the result register that will receive the result of the current conversion. For example, CC3 = 0,
CC2 = 1, CC1 = 1, CC0 = 0 indicates that the result of the current conversion will be in ATD Result Register 6.
If in non-FIFO mode (FIFO = 0) the conversion counter is initialized to zero at the begin and end of the
conversion sequence. If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion
counters wraps around when its maximum value is reached.
Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the
conversion counter even if FIFO=1.
MC9S12XDP512 Data Sheet, Rev. 2.21
144
Freescale Semiconductor
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