MC9S12XD256CAL Datasheet, PDF (864/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.53 Port H Interrupt Flag Register (PIFH)
R
W
Reset
7
PIFH7
0
6
PIFH6
5
PIFH5
4
PIFH4
3
PIFH3
2
PIFH2
0
0
0
0
0
Figure 22-55. Port H Interrupt Flag Register (PIFH)
1
PIFH1
0
0
PIFH0
0
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSH register. To clear this flag, write logic level “1” to the corresponding bit in the
PIFH register. Writing a “0” has no effect.
Table 22-50. PIFH Field Descriptions
Field
Description
7–0
PIFH[7:0]
Interrupt Flags Port H
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a logic level “1” clears the associated flag.
MC9S12XDP512 Data Sheet, Rev. 2.21
866
Freescale Semiconductor