MC9S12XD256CAL Datasheet, PDF (58/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 1 Device Overview MC9S12XD-Family
The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check
is ongoing. This is the case for:
• Power on reset or low-voltage reset
• Clock monitor reset
• Any reset while in self-clock mode or full stop mode
The selected oscillator configuration is frozen with the rising edge of reset.
The pin can be configured to drive the internal system clock ECLKX2.
EXTAL
MCU
C₁
Crystal or
Ceramic Resonator
XTAL
C₂
V_SSPLL
Figure 1-11. Loop Controlled Pierce Oscillator Connections (PE7 = 1)
EXTAL
MCU
XTAL
R_B
R_S
C₁
Crystal or
Ceramic Resonator
C₂
V_SSPLL
Figure 1-12. Full Swing Pierce Oscillator Connections (PE7 = 0)
EXTAL
MCU
XTAL
CMOS-Compatible
External Oscillator
Not Connected
Figure 1-13. External Clock Connections (PE7 = 0)
1.2.3.17 PE6 / MODB / TAGHI — Port E I/O Pin 6
PE6 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is an input with a
MC9S12XDP512 Data Sheet, Rev. 2.21
58
Freescale Semiconductor