MC9S12XD256CAL Datasheet, PDF (590/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 15 Background Debug Module (S12XBDMV2)
Figure 15-14 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could
occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode.
Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being
connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this
case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not
a probable situation, the protocol does not prevent this conflict from happening.
BDM Clock
(Target MCU)
Target MCU
Drives to
BKGD Pin
Host
Drives SYNC
To BKGD Pin
BKGD Pin
At Least 128 Cycles
ACK Pulse
Host and
Target Drive
to BKGD Pin
Host SYNC Request Pulse
High-Impedance
Electrical Conflict
Speedup Pulse
16 Cycles
Figure 15-14. ACK Pulse and SYNC Request Conflict
NOTE
This information is being provided so that the MCU integrator will be aware
that such a conflict could eventually occur.
The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE
BDM commands. This provides backwards compatibility with the existing POD devices which are not
able to execute the hardware handshake protocol. It also allows for new POD devices, that support the
hardware handshake protocol, to freely communicate with the target device. If desired, without the need
for waiting for the ACK pulse.
The commands are described as follows:
• ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse
when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the
ACK pulse as a response.
• ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst
case delay time at the appropriate places in the protocol.
The default state of the BDM after reset is hardware handshake protocol disabled.
All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then
ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data
has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See
Section 15.4.3, “BDM Hardware Commands” and Section 15.4.4, “Standard BDM Firmware Commands”
for more information on the BDM commands.
MC9S12XDP512 Data Sheet, Rev. 2.21
590
Freescale Semiconductor