MC9S12XD256CAL Datasheet, PDF (776/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 20 S12X Debug (S12XDBGV3) Module
20.4.5.3 Trace Buffer Organization
The buffer can be used to trace either from S12XCPU, from XGATE or from both sources. An X prefix
denotes information from the XGATE module, a C prefix denotes information from the S12XCPU.
ADRH, ADRM, ADRL denote address high, middle and low byte respectively. INF bytes contain control
information (R/W, S/D etc.). The numerical suffix indicates which tracing step. The information format
for Loop1 Mode is the same as that of Normal Mode. Whilst tracing from XGATE or S12XCPU only, in
Normal or Loop1 modes each array line contains data from entries made at two separate times, thus in this
case the DBGCNT[0] is incremented after each separate entry. In all other modes DBGCNT[0] remains
cleared whilst the other DBGCNT bits are incremented on each trace buffer entry.
XGATE and S12XCPU COFs occur independently of each other and the profile of COFs for the two
sources is totally different. When both sources are being traced in Normal or Loop1 mode, for each COF
from one source, there may be many COFs from the other source, depending on user code. COF events
could occur far from each other in the time domain, on consecutive cycles or simultaneously. When a COF
occurs in either source (S12X or XGATE) a trace buffer entry is made and the corresponding CDV or XDV
bit is set. The current PC of the other source is simultaneously stored to the trace buffer even if no COF
has occurred, in which case CDV/XDV remains cleared indicating the address is not associated with a
COF, but is simply a snapshot of the PC contents at the time of the COF from the other source.
Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (CDATAL
or XDATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is
always stored to trace buffer byte3 and the byte at the higher address is stored to byte2
Mode
7
XGATE
Detail
CXINF1
CXINF2
S12XCPU
Detail
CXINF1
CXINF2
Both
Other Modes
XINF0
XINF1
XGATE
Other Modes
XINF1
XINF3
S12XCPU
Other Modes
CINF1
CINF3
Table 20-39. Trace Buffer Organization
8-Byte Wide Word Buffer
6
5
4
3
2
1
CADRH1
CADRH2
CADRM1
CADRM2
CADRL1
CADRL2
XDATAH1
XDATAH2
XDATAL1
XDATAL2
XADRM1
XADRM2
CADRH1
CADRH2
CADRM1
CADRM2
CADRL1
CADRL2
CDATAH1 CDATAL1
CDATAH2 CDATAL2
XADRM1
XADRM2
XPCM0
XPCM1
XPCL0
XPCL1
CINF0
CINF1
CPCH0
CPCH1
CPCM0
CPCM1
XPCM1
XPCM3
XPCL1
XPCL3
XINF0
XINF2
XPCM0
XPCM2
CPCH1
CPCH3
CPCM1
CPCM3
CPCL1
CPCL3
CINF0
CINF2
CPCH0
CPCH2
CPCM0
CPCM2
0
XADRL1
XADRL2
XADRL1
XADRL2
CPCL0
CPCL1
XPCL0
XPCL2
CPCL0
CPCL2
MC9S12XDP512 Data Sheet, Rev. 2.21
778
Freescale Semiconductor