MC9S12XD256CAL Datasheet, PDF (600/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 16 Interrupt (S12XINTV1)
16.3.1 Register Descriptions
This section describes in address order all the XINT registers and their individual bits.
Address
Register
Name
Bit 7
6
0x0121
IVBR
R
W
5
4
3
2
IVB_ADDR[7:0]
1
Bit 0
0x0126 INT_XGPRIO R
0
0
0
0
0
W
XILVL[2:0]
0x0127 INT_CFADDR R
W
INT_CFADDR[7:4]
0
0
0
0
0x0128 INT_CFDATA0 R
0
0
0
0
RQST
W
0x0129 INT_CFDATA1 R
0
0
0
0
RQST
W
PRIOLVL[2:0]
PRIOLVL[2:0]
0x012A INT_CFDATA2 R
0
0
0
0
RQST
W
PRIOLVL[2:0]
0x012B INT_CFDATA3 R
0
0
0
0
RQST
W
PRIOLVL[2:0]
0x012C INT_CFDATA4 R
0
0
0
0
RQST
W
PRIOLVL[2:0]
0x012D INT_CFDATA5 R
0
0
0
0
RQST
W
PRIOLVL[2:0]
0x012E INT_CFDATA6 R
0
0
0
0
RQST
W
PRIOLVL[2:0]
0x012F INT_CFDATA7 R
0
0
0
0
RQST
W
PRIOLVL[2:0]
= Unimplemented or Reserved
Figure 16-2. XINT Register Summary
MC9S12XDP512 Data Sheet, Rev. 2.21
600
Freescale Semiconductor