MC9S12XD256CAL Datasheet, PDF (1013/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Table 24-38. PPSP Field Descriptions
Field
Description
7–0
PPSP[7:0]
Polarity Select Port P
0 Falling edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-up device is
connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
1 Rising edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-down device
is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is
used as input.
24.0.5.40 Port P Interrupt Enable Register (PIEP)
R
W
Reset
7
PIEP7
0
6
PIEP6
5
PIEP5
4
PIEP4
3
PIEP3
2
PIEP2
0
0
0
0
0
Figure 24-42. Port P Interrupt Enable Register (PIEP)
1
PIEP1
0
0
PIEP0
0
Read: Anytime.
Write: Anytime.
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated
with Port P.
Table 24-39. PIEP Field Descriptions
Field
Description
7–0
PIEP[7:0]
Interrupt Enable Port P
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
24.0.5.41 Port P Interrupt Flag Register (PIFP)
7
R
PIFP7
W
6
PIFP6
5
PIFP5
4
PIFP4
3
PIFP3
2
PIFP2
1
PIFP1
0
PIFP0
Reset
0
0
0
0
0
0
0
0
Figure 24-43. Port P Interrupt Flag Register (PIFP)
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling
edge based on the state of the PPSP register. To clear this flag, write logic level “1” to the
corresponding bit in the PIFP register. Writing a “0” has no effect.