MC9S12XD256CAL Datasheet, PDF (922/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.5.8 Port D Data Direction Register (DDRD)
R
W
Reset
7
DDRD7
0
6
DDRD6
5
DDRD5
4
DDRD4
3
DDRD3
2
DDRD2
0
0
0
0
0
Figure 23-10. Port D Data Direction Register (DDRD)
1
DDRD1
0
0
DDRD0
0
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 23-11. DDRD Field Descriptions
Field
Description
7–0
DDRD[7:0]
Data Direction Port D — This register controls the data direction for port D. DDRD determines whether each pin
is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes
the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTD after changing the DDRD register.
23.0.5.9 Port E Data Register (PORTE)
7
R
PE7
W
Alt.
Func.
XCLKS
or
ECLKX2
Reset
0
6
PE6
MODB
or
TAGHI
0
5
PE5
MODA
or
RE
or
TAGLO
0
4
PE4
3
PE3
2
PE2
EROMCTL
or
R/W
ECLK
LSTRB
or
or
WE
LDS
0
0
0
1
PE1
0
PE0
IRQ
XIRQ
—¹
—¹
= Unimplemented or Reserved
Figure 23-11. Port E Data Register (PORTE)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
MC9S12XDP512 Data Sheet, Rev. 2.21
924
Freescale Semiconductor