MC9S12XD256CAL Datasheet, PDF (370/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
8.3.2.2 PWM Polarity Register (PWMPOL)
The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the
PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle
and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts
low and then goes high when the duty count is reached.
R
W
Reset
7
PPOL7
0
6
PPOL6
5
PPOL5
4
PPOL4
3
PPOL3
2
PPOL2
0
0
0
0
0
Figure 8-4. PWM Polarity Register (PWMPOL)
1
PPOL1
0
0
PPOL0
0
Read: Anytime
Write: Anytime
NOTE
PPOLx register bits can be written anytime. If the polarity is changed while
a PWM signal is being generated, a truncated or stretched pulse can occur
during the transition
Table 8-2. PWMPOL Field Descriptions
Field
Description
7–0
PPOL[7:0]
Pulse Width Channel 7–0 Polarity Bits
0 PWM channel 7–0 outputs are low at the beginning of the period, then go high when the duty count is
reached.
1 PWM channel 7–0 outputs are high at the beginning of the period, then go low when the duty count is
reached.
8.3.2.3 PWM Clock Select Register (PWMCLK)
Each PWM channel has a choice of two clocks to use as the clock source for that channel as described
below.
R
W
Reset
7
PCLK7
0
Read: Anytime
Write: Anytime
6
PCLKL6
5
PCLK5
4
PCLK4
3
PCLK3
2
PCLK2
0
0
0
0
0
Figure 8-5. PWM Clock Select Register (PWMCLK)
1
PCLK1
0
0
PCLK0
0
MC9S12XDP512 Data Sheet, Rev. 2.21
370
Freescale Semiconductor