MC9S12XD256CAL Datasheet, PDF (521/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

MODFEN
0
0
1
1
Chapter 12 Serial Peripheral Interface (S12SPIV4)
Table 12-2. SS Input / Output Selection
SSOE
0
1
0
1
Master Mode
SS not used by SPI
SS not used by SPI
SS input with MODF feature
SS is slave select output
Slave Mode
SS input
SS input
SS input
SS input
12.3.2.2 SPI Control Register 2 (SPICR2)
7
6
5
4
3
2
R
0
0
0
0
MODFEN BIDIROE
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-4. SPI Control Register 2 (SPICR2)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Table 12-3. SPICR2 Field Descriptions
1
SPISWAI
0
0
SPC0
0
Field
Description
4
MODFEN
3
BIDIROE
1
SPISWAI
0
SPC0
Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and
MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an
input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin
configuration, refer to Table 12-4. In master mode, a change of this bit will abort a transmission in progress and
force the SPI system into idle state.
0 SS port pin is not used by the SPI.
1 SS port pin with MODF feature.
Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer
of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output
buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0
set, a change of this bit will abort a transmission in progress and force the SPI into idle state.
0 Output buffer disabled.
1 Output buffer enabled.
SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
0 SPI clock operates normally in wait mode.
1 Stop SPI clock generation when in wait mode.
Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in Table 12-4. In master
mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
521