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MC9S12XD256CAL Datasheet, PDF (279/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG). | |||
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STW
Store Word to Memory
Chapter 6 XGATE (S12XGATEV2)
STW
Operation
RS â M[RB, #OFFS5]
RS â M[RB, RI]
RS â M[RB, RI]; RI+2 â RI;
RIâ2 â RI; RS â M[RB, RI]1
Stores the content of register RS to memory.
CCR Effects
NZVC
ââââ
N: Not affected.
Z: Not affected.
V: Not affected.
C: Not affected.
Code and CPU Cycles
Source Form
STW RS, (RB, #OFFS5)
STW RS, (RB, RI)
STW RS, (RB, RI+)
STW RS, (RB, -RI)
Address
Mode
IDO5
IDR
IDR+
-IDR
01011
01111
01111
01111
Machine Code
RS
RB
RS
RB
RS
RB
RS
RB
Cycles
OFFS5
PW
RI 0 0 PW
RI 0 1 PW
RI 1 0 PW
1. If the same general purpose register is used as index (RI) and source register (RS), the unmodiï¬ed content of the source
register is written to the memory: RS â M[RB, RSâ2]; RSâ2 â RS
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
279
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