MC9S12XD256CAL Datasheet, PDF (583/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 15 Background Debug Module (S12XBDMV2)
The external host should wait at least for 76 bus clock cycles after a TRACE1 or GO command before
starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM
firmware lookup table and resume execution of the user code. Disturbing the BDM shift register
prematurely may adversely affect the exit from the standard BDM firmware lookup table.
NOTE
If the bus rate of the target processor is unknown or could be changing or the
external wait function is used, it is recommended that the ACK
(acknowledge function) is used to indicate when an operation is complete.
When using ACK, the delay times are automated.
Figure 15-7 represents the BDM command structure. The command blocks illustrate a series of eight bit
times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles
in the high state. The time for an 8-bit command is 8 × 16 target clock cycles.¹
Hardware
Read
Hardware
Write
Firmware
Read
Firmware
Write
GO,
TRACE
8 Bits
AT ~16 TC/Bit
Command
16 Bits
AT ~16 TC/Bit
Address
150-BC
Delay
16 Bits
AT ~16 TC/Bit
Data
Next
Command
Command
Address
150-BC
Delay
Data
Next
Command
48-BC
DELAY
Command
Data
Next
Command
Command
36-BC
DELAY
Data
Next
Command
Command
76-BC
Delay
Next
Command
BC = Bus Clock Cycles
TC = Target Clock Cycles
Figure 15-7. BDM Command Structure
1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 15.4.6, “BDM Serial Interface”
and Section 15.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
583