MC9S12XD256CAL Datasheet, PDF (76/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 1 Device Overview MC9S12XD-Family
1.6.2 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block Guides for register reset states.
1.6.2.1 I/O Pins
Refer to the PIM Block Guide for reset configurations of all peripheral module ports.
1.6.2.2 Memory
The RAM array is not initialized out of reset.
1.7 COP Configuration
The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge
of RESET from the Flash control register FCTL ($0107) located in the Flash EEPROM block. See
Table 1-13 and Table 1-14 for coding. The FCTL register is loaded from the Flash configuration field byte
at global address $7FFF0E during the reset sequence
NOTE
If the MCU is secured the COP timeout rate is always set to the longest
period (CR[2:0] = 111) after COP reset.
Table 1-13. Initial COP Rate Configuration
NV[2:0] in
FCTL Register
000
001
010
011
100
101
110
111
CR[2:0] in
COPCTL Register
111
110
101
100
011
010
001
000
Table 1-14. Initial WCOP Configuration
NV[3] in
FCTL Register
1
0
WCOP in
COPCTL Register
0
1
MC9S12XDP512 Data Sheet, Rev. 2.21
76
Freescale Semiconductor