MC9S12XD256CAL Datasheet, PDF (560/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 14 Voltage Regulator (S12VREG3V3V5)
14.3.2.3 Autonomous Periodical Interrupt Control Register (VREGAPICL)
The VREGAPICL register allows the configuration of the VREG_3V3 autonomous periodical interrupt
features.
R
W
Reset
7
6
5
4
3
2
1
0
0
0
0
APICLK
APIFE
APIE
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-4. Autonomous Periodical Interrupt Control Register (VREGAPICL)
0
APIF
0
Table 14-4. VREGAPICL Field Descriptions
Field
7
APICLK
2
APIFE
1
APIE
0
APIF
Description
Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if
APIFE = 0; APICLK cannot be changed if APIFE is set by the same write operation.
0 Autonomous periodical interrupt clock used as source.
1 Bus clock used as source.
Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer
when set.
0 Autonomous periodical interrupt is disabled.
1 Autonomous periodical interrupt is enabled and timer starts running.
Autonomous Periodical Interrupt Enable Bit
0 API interrupt request is disabled.
1 API interrupt will be requested whenever APIF is set.
Autonomous Periodical Interrupt Flag — APIF is set to 1 when the in the API configured time has elapsed.
This flag can only be cleared by writing a 1 to it. Clearing of the flag has precedence over setting.
Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request.
0 API timeout has not yet occurred.
1 API timeout has occurred.
MC9S12XDP512 Data Sheet, Rev. 2.21
560
Freescale Semiconductor