MC9S12XD256CAL Datasheet, PDF (399/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

9.3.2.2
Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
IIC Frequency Divider Register (IBFD)
R
W
Reset
7
IBC7
0
6
IBC6
5
IBC5
4
IBC4
3
IBC3
2
IBC2
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-4. IIC Bus Frequency Divider Register (IBFD)
Read and write anytime
Table 9-2. IBFD Field Descriptions
1
IBC1
0
0
IBC0
0
Field
7:0
IBC[7:0]
Description
I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and
IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown
in Table 9-3.
IBC5-3
(bin)
000
001
010
011
100
101
110
111
Table 9-3. I-Bus Tap and Prescale Values
IBC2-0
(bin)
000
001
010
011
100
101
110
111
SCL Tap
(clocks)
5
6
7
8
9
10
12
15
SDA Tap
(clocks)
1
1
2
2
3
3
4
4
scl2start
(clocks)
2
2
2
6
14
30
62
126
scl2stop
(clocks)
7
7
9
9
17
33
65
129
scl2tap
(clocks)
4
4
6
6
14
30
62
126
tap2tap
(clocks)
1
2
4
8
16
32
64
128
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
399